If digital circuits operate in synchronization with a clock signal whose frequency is always constant, large noise occurs and the noise has a bad influence to other electronic device. Especially, when a lot of electronic devices are placed in a limited space, for example, in a vehicle, this problem is remarkable. Therefore, various clock generating circuits are proposed for reducing the clock noise by using a spread spectrum technology.
Among the proposed clock generating circuits, it is a general manner to use a PLL (Phase-Locked Loop) circuit having a voltage-controlled oscillator which oscillates with a frequency depending on a voltage added by random noise to generate a spectrum-spread clock signal. However, because the PLL circuit is composed of a mixer, a loop filter, the voltage-controlled oscillator and a divider, there is a likelihood that a circuit volume may be large.